The present invention relates to a semiconductor memory device and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor device for DRAMs (Dynamic Random Access Memories) which includes a memory cell array and a peripheral circuit mounted together on the same chip.
Nowadays, memory cells (DRAM cells) having a stacked capacitor have been developed for use in a 256M bit DRAM and an IG bit DRAM. In most of the DRAM cells, the capacitor is formed after a bit line is formed. Such a structure is called "capacitor-over-bit-line (COB) structure".
The COB structure has a merit in that the capacitor can occupy a large area since the capacitor is not influenced by the formation of the bit line. However, the COB has demerits in that a parasitic capacitance to the bit line is large, and in that it is difficult to form the bit line by use of Al since a self-aligning process is required for the bit line formation.
Because of the aforementioned demerits, the COB structure is not well adapted to the chip (which will be a main-current DRAM chip) consisting of a memory cell array and a peripheral logic circuit (hereinafter referred to as "peripheral circuit") mounted together on the same chip.
On the other hand, if another cell having a bit-line-over-capacitor structure (a capacitor is formed before the bit line) is employed, the aforementioned problems can be overcome. However, if the chip having a memory cell array and a peripheral circuit mounted together thereon, is formed by using the bit-line-over-capacitor structure, a stepped portion is undesirably formed on an upper surface of an interlayer insulating film between the memory cell region and the peripheral circuit region depending upon the presence/absence of a capacitor.
FIGS. 1A-1C show an example of a DRAM having a memory cell array and a peripheral circuit mounted on the same chip and formed by using a cell having the bit-line-over-capacitor structure. In the DRAM shown in these figures, a memory cell region is shown on the left side (101a) of the device and a peripheral circuit region is shown on the right side (101b).
To describe the DRAM more specifically referring to FIG. 1C, a device formation region is surrounded by a field oxidation film 102 which is formed on a silicon substrate 101. In the device formation region, a plurality of MOS transistors each consisting of a gate electrode 103 and source/drain regions 104, are formed. The memory cell region 101a is thus formed. In the memory cell region, a stacked capacitor is formed. The stacked capacitor is formed of a storage node electrode 105, a capacitor insulating film 106, and a plate electrode 107. The storage node electrode 105 is electrically connected to one of the source/drain regions 104 of each of the MOS transistors.
Corresponding to the other source/drain region 104, a bit line contact 110 is formed which is connected to a bit line 109 formed on an interlayer insulating film 108.
In the peripheral circuit region 101b, a gate electrode contact 111 to be connected to the bit line 109 is formed in correspondence with the gate electrode 103 formed on the field oxidation film 102.
Furthermore, a diffusion layer contact 112 to be connected to the bit line 109 is formed corresponding to one of the source/drain regions 104 of the MOS transistor which is formed on the field region.
However, the DRAM thus constructed has a problem. Since the interlayer insulating film 108 is formed over an entire surface after the stacked capacitor is formed in the memory cell portion, as shown in FIG. 1B, a stepped portion 120 is formed in the upper surface of the interlayer insulating film 108 between the memory cell region 101a and the peripheral circuit region 101b depending upon the presence or absence of the capacitor (see FIG. 1C). It is therefore difficult to pattern the bit line 109 with a high accuracy. As mentioned above, the DRAM of a the bit-line-over-capacitor structure has a problem in that the memory cell region is not well-matched with the peripheral circuit region.